1. Field of the Invention
The invention relates generally to semiconductor structures including field effect transistors. More particularly, the invention relates to semiconductor structures including field effect transistors with enhanced performance.
2. Description of the Related Art
Semiconductor structures, which include resistors, transistors, diodes and capacitors, have been successfully scaled to increasingly smaller dimensions over a period of several decades. The scaling of semiconductor structures over several decades has provided both an enhanced functionality of semiconductor circuits, such as logic circuits, and an enhanced capacity of semiconductor products, such as, memory products.
In order to continue to provide increases in semiconductor circuit performance, a recent trend in semiconductor technology has been the fabrication of semiconductor devices, and in particular field effect devices, upon semiconductor substrates having multiple crystallographic orientation regions. By using semiconductor substrates having multiple crystallographic orientation regions, charge carrier mobilities may often be enhanced within the context of particular differing crystallographic orientation region polarities.
Semiconductor substrates having different crystallographic orientation regions do provide a clear charge carrier mobility advantage with respect to fabrication thereon of semiconductor devices having different polarities. However, the fabrication of semiconductor structures that incorporate different crystallographic orientation semiconductor substrate regions is not entirely without problems. In particular, fabricating semiconductor structures within semiconductor substrates that include multiple crystallographic orientation regions is difficult insofar as fabricating the multiple crystallographic orientation regions may not be readily accomplished absent defects therein.
Semiconductor substrates having multiple crystallographic orientation regions, and methods for fabrication thereof, are known in the semiconductor fabrication art.
For example, de Souza et al., in U.S. Patent Pub. No. 2005/0116290, teaches a particular method for fabricating a semiconductor substrate with multiple crystallographic orientation regions. The method utilizes an amorphization of a particular semiconductor layer within a semiconductor structure, and a recrystallization of the particular semiconductor layer with a different crystallographic orientation while using a template layer as a base layer for the recrystallization.
Semiconductor structure and device dimensions are certain to continue to decrease, and as a result thereof semiconductor devices and structures having enhanced performance at decreased dimensions are desirable. Particularly desirable are semiconductor structures that include multiple crystallographic orientation regions that provide enhanced semiconductor device performance.